Run interrupt handlers as untrusted user processes — and still get hardware-grade latency. 15 cycles from interrupt assertion to the first handler instruction, whether the target process is running or asleep.
▶See how it works Interrupt assertion to the first handler instruction in 15 cycles — whether the target process is running or asleep.
DULI delivers an interrupt to its handler in 15 cycles (300 ns at 50 MHz) whether the target process is running or dormant. Intel UINTR and RISC-V-N only take the fast path while the target is scheduled; otherwise they fall back to a kernel path of over 800 cycles.
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Confined by construction
Every user-level interrupt carries a spatial domain (a PMP table entry) and a temporal domain (a hardware execution budget). An out-of-bounds access or an expired budget forces an immediate return to the preempted context — no kernel mediation.
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It preempts the kernel
Handlers can preempt normal threads, the kernel, and other user-level handlers. Register banks give zero-latency context switches; a spill path handles unbounded nesting when the banks run out.
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Microkernel-native
The OS abstraction turns each handler into a run-to-completion hardware thread: int_reg, int_prio, int_ena, and a custom uiret. Integrating the extension into an existing microkernel took about 2% more source lines.
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Five PPA points
From V1 (37 cycles, +23% core area, no new memory port) to V5 (11 cycles modeled, +66% area, IID CAM + banked contexts). Pick the point your silicon budget and latency target can afford.
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Proven in silicon and FPGA
Implemented on Nangate 45 nm with OpenROAD and prototyped on an XC7K480T FPGA. Area is small enough that the lowest-overhead variant adds under 1% to a typical microcontroller die.
A microkernel isolates each component as an unprivileged process. That is where the trouble starts for interrupts: the handler belongs to the component, but kernel forwarding costs an order of magnitude more than a kernel-level interrupt. Putting the handler back into the kernel restores latency and throws the isolation away.
BEFORE
Secure but slow
A user-level handler waits for the kernel to switch domains, save the context, and forward the interrupt. Measured: over 800 cycles.
FAST PATH
Fast but conditional
UINTR-style delivery skips the kernel only while the target is already scheduled. When it is dormant, the slow path returns — a bimodal, unpredictable distribution.
DULI
Fast and bounded
The hardware activates the handler together with its protection domains. 15 cycles, independent of the current process, with the isolation still enforced by hardware.
The same interrupt, four delivery models. Watch where the time goes — and why DULI’s bar stops first.
HWhardware stageSWsoftware stage
Kernel-mediatedtrap → save → schedule → switch → restore
HWInterruptdevice raises IRQ
HWTrapenter the kernel
SWSaveregisters → stack
SWSchedulepick the target
SWSwitchPMP + stack
SWRestoretarget registers
SWHandlerkernel-mode handoff
0…
UINTR-stylefast only while the target is scheduled; otherwise the kernel path
HWInterruptdevice raises IRQ
HWGate passestarget is current
SWHandleruser-level fast path
fast path…
Software fast patha thin kernel prologue, no scheduler
HWInterruptdevice raises IRQ
SWPrologueminimal kernel entry
SWSaveregisters → stack
SWDispatchno PMP switch
SWHandlerkernel-mode run
0…
eBPF (AoT)safe execution — 3.27× native, not a delivery path
HWInterruptdevice raises IRQ
SWeBPF entryenter the runtime
SWeBPF program3.27× native execution
SWReturnback to caller
3.27×…
DULIhardware activates the handler and its domains
HWInterruptdevice raises IRQ
HWIID lookupCAM, in acknowledge
HWParallelPMP · budget · context
SWHandlerunprivileged, confined
0…
Kernel path: two hardware stages, then five software stages in series. UINTR falls back to the same software chain when the target is dormant. DULI: three hardware stages, then the user handler. eBPF is a safe execution model — 3.27× native average execution — not a delivery mechanism.
Schematic timing, not drawn to cycle scale; the numbers on the right are the measured values.
DULI's delivery path contains no kernel code: the hardware identifies the domain, loads PMP and the budget, and banks the interrupted context. The other models are slow for structural reasons: kernel mediation serializes trap, save, schedule, domain switch and restore; UINTR removes those steps only while the target is already scheduled; the software path still saves context and, when the target is dormant, reprograms PMP.
Most user-level interrupt schemes optimize the average case. DULI targets the worst case: the handler runs at the same speed whether its process is the current one or has been switched out for hours.
V1–V5 latency is the hardware model; V5 measures 15 cycles end-to-end on FPGA.
The five variants resolve one bottleneck at a time: table lookup, context stacking, bus contention, and finally the IID lookup itself. The design-space page walks through all five with area, power and latency numbers.