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DULIDeterministic user‑level interrupts

Run interrupt handlers as untrusted user processes — and still get hardware-grade latency. 15 cycles from interrupt assertion to the first handler instruction, whether the target process is running or asleep.

▶See how it works Interrupt assertion to the first handler instruction in 15 cycles — whether the target process is running or asleep.
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The trade-off DULI removes ​

A microkernel isolates each component as an unprivileged process. That is where the trouble starts for interrupts: the handler belongs to the component, but kernel forwarding costs an order of magnitude more than a kernel-level interrupt. Putting the handler back into the kernel restores latency and throws the isolation away.

BEFORE

Secure but slow

A user-level handler waits for the kernel to switch domains, save the context, and forward the interrupt. Measured: over 800 cycles.

FAST PATH

Fast but conditional

UINTR-style delivery skips the kernel only while the target is already scheduled. When it is dormant, the slow path returns — a bimodal, unpredictable distribution.

DULI

Fast and bounded

The hardware activates the handler together with its protection domains. 15 cycles, independent of the current process, with the isolation still enforced by hardware.

How it works ​

Interrupt delivery, animated

The same interrupt, four delivery models. Watch where the time goes — and why DULI’s bar stops first.

HWhardware stageSWsoftware stage
Kernel-mediatedtrap → save → schedule → switch → restore
HWInterruptdevice raises IRQ
HWTrapenter the kernel
SWSaveregisters → stack
SWSchedulepick the target
SWSwitchPMP + stack
SWRestoretarget registers
SWHandlerkernel-mode handoff
0…
UINTR-stylefast only while the target is scheduled; otherwise the kernel path
HWInterruptdevice raises IRQ
HWGate passestarget is current
SWHandleruser-level fast path
fast path…
Software fast patha thin kernel prologue, no scheduler
HWInterruptdevice raises IRQ
SWPrologueminimal kernel entry
SWSaveregisters → stack
SWDispatchno PMP switch
SWHandlerkernel-mode run
0…
eBPF (AoT)safe execution — 3.27× native, not a delivery path
HWInterruptdevice raises IRQ
SWeBPF entryenter the runtime
SWeBPF program3.27× native execution
SWReturnback to caller
3.27×…
DULIhardware activates the handler and its domains
HWInterruptdevice raises IRQ
HWIID lookupCAM, in acknowledge
HWParallelPMP · budget · context
SWHandlerunprivileged, confined
0…

Kernel path: two hardware stages, then five software stages in series. UINTR falls back to the same software chain when the target is dormant. DULI: three hardware stages, then the user handler. eBPF is a safe execution model — 3.27× native average execution — not a delivery mechanism.

Schematic timing, not drawn to cycle scale; the numbers on the right are the measured values.

DULI's delivery path contains no kernel code: the hardware identifies the domain, loads PMP and the budget, and banks the interrupted context. The other models are slow for structural reasons: kernel mediation serializes trap, save, schedule, domain switch and restore; UINTR removes those steps only while the target is already scheduled; the software path still saves context and, when the target is dormant, reprograms PMP.

One latency, not two ​

Interrupt latency: target running vs. dormant (cycles, lower is better)target runningtarget dormant0200400600800Kernel-mediated>800>800Software fast path80120DULI · V51515UINTR-style delivery is fast only while the target is scheduled; when it is dormant it falls back to the kernel path, so its worst case is the kernel's.
Schemetarget runningtarget dormant
Kernel-mediated>800>800
Software fast path80120
DULI · V51515

Most user-level interrupt schemes optimize the average case. DULI targets the worst case: the handler runs at the same speed whether its process is the current one or has been switched out for hours.

Pick your point on the curve ​

Area vs. latency (core area overhead vs. interrupt latency)0102030400%20%40%60%Core area overhead (%)Interrupt latency (cycles)BaseV1V2V3V4V5
VariantArea overheadLatency (cycles)
Base0%5
V1+23%37
V2+27%29
V3+48%17
V4+51%14
V5+66%11
V1–V5 latency is the hardware model; V5 measures 15 cycles end-to-end on FPGA.

The five variants resolve one bottleneck at a time: table lookup, context stacking, bus contention, and finally the IID lookup itself. The design-space page walks through all five with area, power and latency numbers.

Built for systems that cannot miss a deadline ​

MOTION

Pulse-train output

PLC and servo drives need at least 20 kHz. DULI sustains up to ~300 kHz and keeps jitter below 5% at 100 kHz while an unrelated process interleaves.

CONSOLIDATION

Real-time + best-effort

A Modbus-RTU foreground at 2 Mbps and an image-recognition background: DULI loses under 17% FPS at 1 Mbps, where kernel forwarding collapses.

SECURITY

Untrusted handlers

A malicious handler that reads foreign memory or loops forever is terminated by the same hardware that delivered it. Faults stay inside the component.

See the use cases →

A research hardware extension from Shandong University.

DULI·Deterministic user-level interrupts·Shandong University